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pll frequency synthesizer adf4107 features 7.0 gh z bandw i dth 2.7 v to 3.3 v p o wer supply separate charge pump supply (v p ) allows extended t u ning voltage in 3 v s y stems programmable dua l -modulus prescaler 8/9, 16/17, 32/33, 64/65 programmable charge pump currents programmable antibacklash p u lsewidth 3-wire seri al in terface analo g and d i gital lo ck de tect hardware and software power-down mode applic ati o ns broadband wireless access satellite syste m s instrumentation wireless lans base stations f o r wireless radi o general description the ad f4107 f r eq uen c y sy n t hesizer can be us ed t o im p l em en t lo ca l o s ci l l a t o r s in t h e u p -c o n ve rsio n a nd do w n -co n versio n s e c t io n s o f wir e les s r e cei v ers and tra n smi t t e rs. i t co n s is ts o f a lo w-n o is e dig i t a l pfd (phas e f r e q uen c y de t e c t or), a p r e c isio n c h ar g e pu m p , a pro g r a m m a bl e re f e re nc e d i v i d e r , pro g r a m m a bl e a an d b co u n t e rs, a n d a d u al-mo d u l us p r es caler (p/p + 1). th e a (6-b i t ) and b (13-b i t) co un t e rs, in co n j un c t io n wi th t h e d u al- m o d u l u s p r es ca ler (p/p + 1), im p l em en t an n divider (n = b p + a). i n addi tio n , the 14-b i t r e f e r e n c e co un t e r (r co un t e r), al lo ws s e le c t ab le r e fin f r e q uen c ies a t t h e p f d in p u t. a com p le t e p ll (p has e -l o c k e d lo o p ) can be im p l e m e n t e d if th e sy n t h e sizer is us ed wi th an ext e r n al lo o p f i l t er a nd v c o (v ol ta g e con t r o l l ed os cil l a t o r ). i t s v e r y hig h band wid t h m e a n s t h a t f r e q ue n c y do ub lers can b e elimin a t e d i n ma n y hi g h f r e q uen c y sys t e m s, sim p lif y in g sys t em a r c h i t e c t u r e a nd re d u c i ng c o st . func tio n a l block di agram clk data le ref in rf in a rf in b 24-bit input register sd out av dd dv dd ce agnd dgnd 14-bit r counter r counter latch 22 14 function latch a, b counter latch from function latch prescaler p/p + 1 n = bp + a load load 13-bit b counter 6-bit a counter 6 19 13 m3 m2 m1 mux sd out av dd high z muxout cpgnd r set v p cp phase frequency detector lock detect reference charge pump current setting 1 adf4107 cpi3 cpi2 cpi1 cpi6 cpi5 cpi4 current setting 2 fi g u r e 1 . rev. 0 in fo rmation fur n ished by an al o g d e v i c e s is believed t o be accurate an d r e liable. how e ver, no r e spon sibili ty is assumed by anal og de vices fo r its use, nor for a n y i n fri n geme nt s of p a t e nt s or ot h e r ri g h t s o f th ird parties that m a y res u lt fro m its use . s p ecificatio n s subj ec t to chan ge witho u t n o tice. no licen s e is g r an te d b y implicatio n or ot h e rwi s e u n de r any p a t e nt or p a t e nt ri ght s of a n al og de vi c e s. tra d emark s a n d registered tra d ema r ks are the proper ty of th eir respectiv e co mpan ies. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2003 analog de vices, i n c. al l r i ght s r e ser v ed .
adf4107 table of conte n ts ad f4107s p ecif ica t ion s ................................................................ 3 t i min g c h a r ac ter i s t ics ..................................................................... 5 a b s o l u t e m a xim u m r a t i n g s ............................................................ 5 p i n c o nf igura t io n s an d f u n c t i onal d e s c r i p t io ns ........................ 6 t y p i cal p e r f o r ma n c e c h a r ac t e r i s t ics ............................................. 7 f u n c t i o n al d e s c r i p t io n .................................................................... 9 refer e nce i n p u t s t a g e ................................................................... 9 rf i n p u t s t a g e ............................................................................... 9 p r es caler (p/p + 1) ........................................................................ 9 a an d b c o un t e rs ......................................................................... 9 r c o un t e r ...................................................................................... 9 p h as e f r e q ue n c y d e t e c t o r an d c h a r g e pum p ........................ 10 mux o ut and l o c k d e t e c t ...................................................... 10 i n p u t s h if t reg i s t er ..................................................................... 10 l a t c h s u mma r y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 refer e nce c o un t e r l a t c h m a p . ................................................. 12 ab c o un t e r l a tc h m a p . ............................................................ 13 f u n c t i o n l a t c h m a p . .................................................................. 14 i n i t ializa t i o n l a t c h m a p . ........................................................... 15 f u n c t i o n l a t c h ............................................................................ 16 i n i t ializa t i o n l a t c h ..................................................................... 17 a p plica t ion s ..................................................................................... 18 l o cal o s cil l a t o r fo r lmds b a s e s t a t io n t r a n s m i t t e r . ........... 18 i n t e r f acin g ................................................................................... 19 pcb d e sig n g u ide l in es fo r c h i p s c ale p a c k a g e .................... 19 o u t l in e dim e n s io n s ....................................................................... 20 es d c a u t ion .................................................................................... 20 or der i n g g u ide ............................................................................... 20 revision history rev i s i o n 0: i n i t ial v e r s i o n rev. 0 | page 2 of 2 0
adf4107 adf4107?specifications ta bl e 1. (av dd = dv dd = 3 v 10%, av dd v p 5.5 v, agn d = dgnd = c p gnd = 0 v, r se t = 5.1 k?, dbm referred to 50 ?, t a = t ma x to t min , unl e ss otherwise note d.) p a r a m e t e r b version 1 b chips 2 (typ) u n i t t e s t condition s / c o m m e n t s rf charac ter i stics rf input freq u ency (rf in ) 3 1.0/7.0 1.0/7.0 ghz min/max see figure 18 fo r input circuit. rf input sensitivity 5/+5 5/+5 dbm min/max maximum allowable prescaler output freq u ency 4 3 0 0 3 0 0 m h z m a x refin ch arac t e ristics refin input frequency 20/250 20/250 mhz min/max for f 20 mhz, use dc-coupled square wave (0 to v dd ). refin input sensitivity 5 0 . 8 / v dd 0 . 8 / v dd v p-p min/ma x ac-coupled wh en dc-coupled, 0 to v dd , max (c mos compatible). refin input capacitance 10 10 pf max refin input cur r ent 100 100 a max phase de tec t or phase detector frequency 6 1 0 4 1 0 4 m h z m a x charge pu mp programmable see figure 25. i cp sink/source high value 5 5 ma typ with r set = 5.1 k low value 625 625 a typ absolute accuracy 2.5 2.5 % typ with r set = 5.1 k r set range 3.0/11 3.0/11 k typ see figure 25. i cp three-state leakage 1 1 na typ sink and source current matching 2 2 % typ 0.5 v ? v cp ? v p 0.5 v i cp vs. v cp 1.5 1.5 % typ 0.5 v ? v cp ? v p 0.5 v i cp vs. temperature 2 2 % typ v cp = v p /2 logic inputs v ih , input hi gh voltage 1.4 1.4 v min v il , input low voltage 0.6 0.6 v max i inh , i inl , input current 1 1 a max c in , input capacitance 10 10 pf max logic outputs v oh , output hig h voltage 1.4 1.4 v min open-drain o utput chosen 1 k pull-up resist or to 1.8 v. v oh , output hig h voltage v dd 0.4 v dd 0.4 v min cmos output c h osen. i oh 1 0 0 1 0 0 a m a x v ol , output low voltage 0.4 0.4 v max i ol = 500 a power suppli e s av dd 2.7/3.3 2.7/3.3 v min/v max dv dd a v dd a v dd v p a v dd / 5 . 5 a v dd /5.5 v min/v max av dd ? v p ?5.5v i dd 7 (ai dd + di dd ) 17 15 ma max 15 ma typ i p 0 . 4 0 . 4 m a m a x t a = 25c pow e r-down mode 8 (ai dd + di dd ) 1 0 1 0 a t y p rev. 0 page 3 of 2 0
adf4107 rev. 0 | page 4 of 20 parameter b version 1 b chips 2 (typ) unit test conditions/comments noise characteristics adf4107 phase noise floor 9 ?174 ?174 dbc/hz typ @ 25 khz pfd frequency ?166 ?166 dbc/hz typ @ 200 khz pfd frequency ?159 ?159 dbc/hz typ @ 1 mhz pfd frequency phase noise performance 10 @ vco output 900 mhz output 11 ?93 ?93 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency 6400 mhz output 12 ?76 ?76 dbc/hz typ @ 1 khz offset and 200 khz pfd frequency 6400 mhz output 13 ?83 ?83 dbc/hz typ @ 1 khz o ffset and 1 mhz pfd frequency spurious signals 900 mhz output 11 ?90/?92 ?90/?92 dbc typ @ 200 kh z/400khz and 200 khz pfd frequency 6400 mhz output 12 ?65/?70 ?65/?70 dbc typ @ 200 kh z/400khz and 200 khz pfd frequency 6400 mhz output 13 ?70/?75 ?70/?75 dbc typ @ 1 mhz/2mhz and 1 mhz pfd frequency 1 operating temperature range (b version) is ?40c to +85c. 2 the b chip specifications are given as typical values. 3 use a square wave for lower frequencies, below the minimum stated. 4 this is the maximum operating frequency of the cmos counters. the prescaler value should be chosen to ensure that the rf input is divided down to a frequency that is less than this value. 5 av dd = dv dd = 3 v. 6 guaranteed by design. sample tested to ensure compliance. 7 t a = 25c; av dd = dv dd = 3 v; p = 32; rf in = 7.0 ghz. 8 t a = 25c; av dd = dv dd = 3.3 v; r = 16383; a = 63; b = 891; p = 32; rf in = 7.0 ghz. 9 the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 2 0logn (where n is the n divider value). 10 the phase noise is measured with the eval-adf4107e b1 evaluation board and the hp8562e spec trum analyzer. the spectrum analyzer provides the refin for the synthesizer (f refout = 10 mhz @ 0 dbm). 11 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 900 mhz; n = 4500; loop b/w = 20 khz. 12 f refin = 10 mhz; f pfd = 200 khz; offset frequency = 1 khz; f rf = 6400 mhz; n = 32000; loop b/w = 20 khz. 13 f refin = 10 mhz; f pfd = 1 mhz; offset frequency = 1 khz; f rf = 6400 mhz; n = 6400; loop b/w = 100 khz.
adf4107 timing characteristics ta bl e 2. (av dd = dv dd = 3 v 10%, av dd v p 5.5 v, agn d = dgnd = c p gnd = 0 v, r se t = 5.1 k?, dbm referred to 50 ?, t a = t ma x to t min , unle ss othe rwise note d.) 1 p a r a m e t e r l i m i t 2 (b version) unit test condition s /comments t 1 10 ns min data to clock setup time t 2 10 ns min data to clock hold time t 3 25 ns min clock high duration t 4 25 ns min clock low duration t 5 10 ns min clock to le setup time t 6 20 ns min le pulsewidth 1 guarante e d by d e sign but no t pro d uctio n te s t e d . 2 opera t i n g t e m p era t ure ra n g e (b ver s i o n ) i s C40 c t o +85 c. clock db22 db2 data le t 1 le db23 (msb) t 2 db1 ( c o n t r o l bi t c 2 ) db0 (lsb) (control bit c1) t 3 t 4 t 6 t 5 f i g u re 2. ti ming d i ag r a m absolute maximum ratings ta bl e 3. (t a = 25c, unless otherwise n o ted.) p a r a m e t e r r a t i n g av dd to gnd 1 C0.3 v to +3.6 v av dd to dv dd C0.3 v to +0.3 v v p to gnd C0.3 v to +5.8 v v p to av dd C0.3 v to +5.8 v digital i/o voltage to gnd C0.3 v to v dd + 0.3 v analog i/o voltage to gnd C0.3 v to v p + 0. 3 v refin, rf in a, rf in b to gnd C0.3 v to v dd + 0.3 v operating tem p erature range industrial (b version) C40c to +85c storage temperature range C65c to +125c maximum junction temperature 150c tssop ja ther mal impedance 150.4c/w csp ja thermal impedance 122c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c t r ansistor coun t c m o s 6 4 2 5 b i p o l a r 3 0 3 s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s r a t i ng o n ly ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . this de vice is a hig h p e r f o r ma n c e rf in t e g r a t e d cir c ui t wi t h an e s d r a t i ng of < 2 k v , a n d it i s e s d s e ns it ive. pr op e r pre c aut i on s s h o u ld b e ta k e n f o r ha n d lin g and as s e m b l y . 1 gnd = a g nd = dgnd = 0 v. rev. 0 | page 5 of 2 0
adf4107 rev. 0 | page 6 of 2 0 pin conf igurations and f u ncti ona l descriptions r set cp cpgnd agnd muxou t le data clk ce dgnd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 rf in b rf in a av dd ref in v p dv dd adf4107 top view (not to scale) tssop f i gur e 3 . adf4 10 7 tssop ( t o p vi e w ) 15 muxout 14 le 13 data 12 clk cpgnd 1 agnd 2 agnd 3 20 c p 11 ce 6 7 8 dg nd 9 dg nd 1 0 4 5 19 18 17 16 rf in b rf in a r set v p dv dd dv dd pin 1 indicator top view adf4107 av dd av dd ref in csp (chip scale package) f i gur e 4 . adf4 10 7 chi p s c al e p a c k a g e ta bl e 4. pin functi onal d e scr i pt ions m n e m o n i c f u n c t i o n r set connecting a resistor between this pin and cpgnd sets the maximum charge pump output cu r r ent. the nomin al voltage potential at the r set pin is 0.66 v. t h e relationshi p between i cp an d r set is se t max cp r i 5 . 25 = so, with r set = 5.1 k?, i cp max = 5 ma. cp charge pump output. when en abled, this pin p r ovides i cp to the ex ternal loop filter, which in t u rn drives the external vco. cpgnd charge pump ground. this is the ground return path for the charge pump. agnd analog ground. t h is is the ground return path of the presca ler. rf in b complementary input to the rf prescaler . t h is p o int must be d e coupled to the ground plane w i th a small bypa ss cap a citor, typically 100 pf. see figure 18. rf in a input to the rf prescaler. this small sig n al input is ac-coupled to the ex ternal v c o. av dd analog power s u pply. this voltage may rang e from 2.7 v to 3.3 v. decoupling capaci tor s to the anal og ground plane should be pla c ed as clo s e as possible to this pin. av dd must be the same value as dv dd . ref in reference input. this is a cmos in put with a nominal threshold of v dd /2 and a dc equivale nt input resistance of 100 k?. see figure 17. this input can be driven from a ttl or cmos crystal oscill ator or it can be ac-coup l ed. d g n d d i g i t a l g r o u n d . ce chip enab le. a l o gic low on this pin po we rs down the device an d puts the charge pump output i n to three-state mode. taking the pin high will power up the device, dependin g on the status of the power-do w n bit, f2. clk se ria l cl oc k in put. th is s e ria l c l oc k is us ed to clock in the serial da ta to the registers. the data is latched into the 24-bit shift register on the clk rising edge. this input is a high impedance cmos input. data serial data inpu t. the serial data is lo aded msb first with the two lsbs being the c o ntrol bits. this input is a high impedance cmos input. le load enable, c m os input. when le goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the c o ntrol bits. muxout t h is multiplexer output allows e i ther the lock detect, the scaled rf, or the scal ed reference frequ e ncy to be accessed externally. dv dd digital power s u pply. this may range from 2. 7 v to 3.3 v. decoupling ca pacitors to the digital g r ou nd plane s h o u ld be placed as clo s e as pos si ble to this pin. d v dd must be the same value as av dd . v p charge pump power supply. this voltage should be greater than or eq ual to v dd . in systems wh ere v dd is 3 v, it can be set to 5 v and used to dr ive a vco with a tuning range of up to 5 v.
adf4107 typical perf orm ance cha r acte ristics f i gure 5 . p a r a m e t e r d a ta fo r the rf input 0 ?30 ?5 ?10 ?25 ?20 ?15 01 2 4 6 35 rf input frequency ? ghz rf input power ? d b m 7 v dd = 3v v p = 3v t a = +85 o c t a = ? 40 o c t a = +25 o c f i g u re 6. input s e n s it iv it y 0 ?60 ?2khz ?10 ?50 ?70 ?90 ?30 ?40 ?80 ?20 +2khz 900mhz ?1khz +1khz ?100 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds averages = 10 ? 93.0dbc/hz frequency output power ? db ref level = ? 14.3dbm f i gure 7. p h ase n o i s e (90 0 m h z, 2 0 0 kh z, 20 kh z) 100hz 1mhz ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?120 ?130 ?140 frequency offset from 900mhz carrier p has e nois e ? dbc/hz 10db/div r l = ? 40dbc/hz rms noise = 0.36 o f i gure 8. integr ate d p h ase no ise ( 9 0 0 mh z, 20 0 k h z, 2 0 k h z) 0 ?60 ?10 ?50 ?70 ?90 ?30 ?40 ?80 ?20 ? 100 output power ? db ref level = ? 14.0dbm ?400khz +400khz 900mhz ? 200khz +200khz frequency v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res bandwidth = 1khz video bandwidth = 1khz sweep = 2.5 seconds averages = 30 ? 91.0dbc/hz f i gure 9. refe r e n c e spurs (9 00 mh z , 2 0 0 kh z, 2 0 k h z) 0 ?60 ?10 ?50 ?70 ?90 ?30 ?40 ?80 ?20 ?100 output power ? db ref level = ? 10dbm ? 2khz +2khz 6400mhz ? 1khz +1khz frequency v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 1mhz loop bandwidth = 100khz res bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds averages = 10 ? 83.0dbc/hz f i gure 10. phase n o ise (6. 4 g h z, 1 m h z, 1 0 0 kh z) rev. 0 page 7 of 2 0
adf4107 100hz 1mhz ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 ?110 ?120 ?130 ?140 frequency offset from 6400mhz carrier p has e nois e ? dbc/hz 10db/div r l = ? 40dbc/hz rms noise = 1.85 o f i gure 11. integ r ated p h ase n o ise (6. 4 gh z, 1 m h z, 1 0 0 k h z) 0 ?6 0 ?1 0 ?5 0 ?7 0 ?9 0 ?3 0 ?4 0 ?8 0 ?2 0 ?100 outp ut p o w e r ? db ref level = ? 10dbm ?2mhz +2mhz 6400mhz ?1mhz +1mhz frequency v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 1mhz loop bandwidth = 100khz res bandwidth = 1khz video bandwidth = 1khz sweep = 13 seconds averages = 1 ?65.0dbc/hz ? 66.0dbc/hz f i g u re 12. r e f e rence spurs ( 6 .4 gh z, 1 m h z, 10 0 k h z) ?60 ?70 ?100 ?40 100 ?20 0 20 40 60 80 ?80 ?90 v dd = 3v v p = 3v temperature ? o c p has e nois e ? dbc/hz f i gure 13. phase n o ise (6. 4 g h z, 1 m h z, 1 0 0 kh z) v s . t e m p er atu r e ?5 ?15 ?45 01 2 3 4 ?25 ?35 tuning voltage ? v firs t re fe re nce s p u r ? dbc 5 ?55 ?85 ?65 ?75 ?105 ?95 v dd = 3v v p = 5v f i gure 14. r e ference spurs v s . v tu ne (6 . 4 gh z, 1 m h z, 10 0 kh z) ?120 ?130 ? 180 10k 100m 100k 1m 10m ?140 ?150 ?160 ?170 phase detector frequency ? hz p has e nois e ? dbc/hz v dd = 3v v p = 5v f i g u re 15. phas e n o is e (r ef e rred t o c p out p ut ) v s . pfd f r e q uenc y 6 5 ?6 0 2.0 0.5 1.0 1.5 4 3 2 1 v cp ? v i cp ? ma 0 ?1 ?2 ?3 ?4 ?5 4.0 2.5 3.0 3.5 5.0 4.5 v p = 5v i cp settling = 5ma f i gure 1 6 . char ge p u m p o u tput ch a r act e ri sti c s rev. 0 | page 8 of 2 0
adf4107 rev. 0 | page 9 of 2 0 functional description ref e renc e input s t ag e the r e fer e n c e i n p u t s t a g e is sho w n i n f i gur e 1 7 . sw1 an d s w 2 a r e n o r m al l y clos e d s w i t ch es. sw3 is n o r m al l y o p en. w h e n p o w e r - do w n is i n i t ia te d , sw3 is clo s e d a nd s w 1 a nd sw2 a r e o p ene d . this ens u r e s t h a t t h er e is n o lo adin g o f t h e ref in pi n on p o we r - d o w n . 100k ? nc ref in nc no sw1 sw2 buffer sw3 to r counter power-down control f i gure 17. r e ference input stag e rf inp u t s t ag e the rf in p u t st a g e is sh o w n in f i gur e 18. i t is f o l l o w ed b y a 2 - st ag e l i m i t i n g am pl i f i e r to ge n e r a te t h e c m l c l o c k l e vel s n e ed ed f o r t h e p r e s c a l e r . 500 ? 1.6v 500 ? agnd bias generator rf in a rf in b av dd f i g u re 18. r f input st ag e prescaler ( p /p + 1) the d u al- m o d u l us p r es caler (p/p + 1), alo n g wi t h t h e a and b co un ters, enable s t h e l a rge divisi o n r a t i o , n, to b e r e a l ize d (n = bp + a). th e d u al - m o d u l us p r es caler , o p era t in g a t cml le vels, t a k e s t h e clo c k f r o m t h e rf in p u t st a g e and divide s i t do wn t o a ma n a ge a b le f r e q uen c y fo r t h e cmos a an d b co un t e rs. th e p r es caler is p r og ra mma b l e . i t ca n be s e t in s o f t wa r e t o 8/9, 16/17, 32/33, o r 64/65. i t is bas e d o n a s y nc h r onou s 4 / 5 c o re. a m i n i m u m d i v i d e r a t i o i s p o ss ibl e f o r f u l l y co n t iguo us o u t p u t f r e q ue ncies. this min i m u m is deter m i n e d b y p , t h e p r es ca ler v a l u e, a nd is g i ve n b y : (p 2 C p). a and b counters the a an d b c m os co un t e rs c o m b i n e w i t h t h e d u a l - m o d u l us p r escaler t o allo w a wid e ran g in g d i visio n ra t i o in t h e p l l f eed ba ck co un t e r . t h e co un t e r s a r e s p eci f i e d t o w o r k w h en t h e p r es caler o u t p u t is 300 mh z o r les s . th us, wi th an rf in p u t f r eq uen c y o f 4.0 gh z, a p r es caler val u e o f 16/17 is valid b u t a val u e o f 8/9 is no t valid . pulse swallo w function the a an d b coun t e rs, in con j u n c t ion wi t h the d u al -m o d u l us p r es caler , mak e i t p o s s ib le t o g e n e ra t e o u t p u t f r eq uen c ies tha t a r e s p a c ed o n l y b y th e r e f e r e n c e f r eq ue n c y d i v i d e d b y r . th e eq ua ti o n f o r th e v c o f r eq uen c y i s a s f o ll o w s : () [] r f a b p f refin vco + = f vc o o u t p u t f r e q ue nc y o f ext e r n al v o l t a g e con t r o l l e d oscilla t o r ( v co). p p r es et m o d u l u s o f d u al- m o d u l u s p r es caler (8/9, 16/17, et c.). b pr es et divide r a t i o o f b i na r y 13-b i t co un ter (3 t o 8191). a pr es et divide r a t i o o f b i na r y 6-b i t swa l lo w co u n ter (0 t o 63). f refin e x te r n a l re f e re nc e f r e q u e nc y o s c i l l a t or . load load from rf input stage prescaler p/p + 1 13-bit b counter to pfd 6-bit a counter n divider modulus control n = bp + a f i gure 19. a and b counters r co unter t h e 14-b i t r co un t e r all o w s th e i n p u t r e f e r e n c e f r eq ue n c y t o be divide d do w n to p r o d uce t h e r e fer e n c e clo c k to t h e phas e f r eq uen c y det e c t o r (p fd). di vis i o n ra tios f r o m 1 t o 16,383 a r e allo w e d .
adf4107 phase frequen c y detec t or and charg e pump the phas e f r e q uen c y dete c t o r (p fd) t a k e s in pu ts f r o m t h e r co un ter and n c o un ter (n = bp + a) a nd p r o d uces a n o u t p u t prop or t i on a l to t h e ph a s e a n d f r e q u e nc y d i f f e r e n c e b e t w e e n th em . f i gur e 20 i s a si m p li f i e d s c h e ma ti c. th e pfd i n c l ud e s a p r og ra mma b l e de l a y e l e m e n t t h a t con t r o ls t h e wi d t h o f t h e a n t i b a ckl a sh p u ls e . this p u ls e e n s u r e s t h a t t h ere is n o de ad zone in t h e p f d t r ansfer f u n c t i o n and minimi zes phas e n o is e and re f e re nc e spu r s . t w o bit s i n t h e re f e re nc e c o u n t e r l a tc h , a b p 2 a nd a b p1, co n t r o l t h e w i d t h o f t h e p u ls e . s e e f i gur e 23. hi hi d1 d2 q1 q2 clr1 clr2 cp u1 u2 up down abp2 abp1 cpgnd u3 r divider programmable delay n divider v p charge pump f i gur e 2 0 . p f d simpl i f ie d s c hema ti c and t i mi ng (in l o c k ) m u xo ut a n d lock de te ct the o u t p u t m u l t i p lexer o n th e ad f4107 al lo w s th e us er t o acces s va r i o u s i n t e r n al p o i n ts on t h e chi p . th e s t a t e o f mux o ut is co n t r o l l ed b y m3, m2, a nd m1 in t h e f u n c tio n la t c h. f i gur e 25 s h o w s t h e f u l l tr u t h ta b l e . f i gur e 21 s h o w s t h e mu x o u t s e c t i o n in b l o c k di a g r a m fo r m . lock detect mux o ut can be p r ogra mm e d f o r tw o typ e s o f lo c k d e t e ct: dig i t a l lo ck de te c t a nd a n a l o g lo ck dete c t . dig i tal lo ck detec t is ac ti v e hig h . w h en t h e lo ck det e c t p r ecisio n ( l dp ) b i t i n t h e r c o u n te r l a tc h i s s e t to 0 , di g i t a l l o ck de t e c t i s s e t hig h w h e n t h e phas e er r o r o n t h r e e co ns e c ut i v e phas e det e c t o r (p d) c y c l es is les s tha n 15 n s . w i t h ldp s e t t o 1, f i v e co n s ec u t i ve c y c l es o f les s tha n 15 n s a r e r e q u ir e d t o s e t t h e lo ck det e c t . i t wi l l st a y s e t hig h u n t i l a phas e er r o r o f g r e a t e r t h a n 25 n s is det e c t e d o n an y s u bs e q uen t p d c y c l e . the n-c h a n ne l o p en-dra in a n al og lo c k det e c t sh o u ld be op e r a t e d w i t h a n e x te r n a l pu l l - u p re s i stor of 1 0 k ? no m i n a l. w h e n l o ck h a s been d e t e ct e d , th i s o u t p u t w i ll be hi gh wi th n a r r o w , l o w - g o i n g p u l s e s . dgnd dv dd control mux analog lock detect digital lock detect r counter output n counter output sdout muxout f i g u re 21. m u x o u t ci r c u i t input shif t register the ad f4107 dig i tal s e c t io n inc l udes a 24-b i t in p u t s h if t r e g i s t er , a 14-b i t r co un t e r , an d a 19-b i t n co un t e r , co m p r i sin g a 6-b i t a co un ter a nd a 13 -b i t b c o un t e r . da t a is clo c k e d in t o the 24-b i t s h if t r e g i s t er o n each r i sin g edg e o f cl k. the da t a is clo c k e d i n ms b f i rst. d a t a is t r an sfer r e d f r o m th e shif t r e g i st er to one of f o u r l a tche s o n t h e r i s i ng e d ge of l e . t h e d e st i n a t i o n la t c h is de t e r m in e d b y t h e s t a t e o f t h e tw o con t rol b i ts (c2, c1) in t h e s h if t r e g i st er . th es e a r e t h e tw o ls bs, d b 1 a nd d b 0, as s h own in t h e timin g dia g ra m of f i gur e 2. th e t r u t h ta b l e f o r t h e s e bit s i s s h ow n i n t a bl e 5 . fi g u re 2 2 show s a su m m a r y of how t h e l a tc he s are pro g r a m m e d . ta bl e 5. c2, c1 truth ta bl e control bits c 2 c 1 data latch 0 0 r c o u n t e r 0 1 n counter (a an d b) 1 0 function latch (including prescaler) 1 1 i n i t i a l i z a t i o n l a t c h rev. 0 | page 10 of 20
adf4107 latch su mmary db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 abp1 abp2 t1 t2 ldp db21 db22 db23 00 x db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 a6 db21 db22 db23 g1 x x db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) f1 pd1 m1 m2 m3 f3 p1 p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4 f5 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 d b 8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (1) f1 pd1 m1 m2 m3 f3 p1 p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4 f5 reference counter latch reserved lock de te ct pr ec ision test mode bits anti- backlash width 14-bit reference counter control bits reserved 13-bit b counter 6-bit a counter control bits n counter latch cp gain function latch prescaler value pow e r - down 2 current setting 2 current setting 1 timer counter control fastlock mo de fastlock e nable cp thre e - sta t e pd p o larity muxout control pow e r - down 1 counte r r eset control bits prescaler value pow e r - down 2 current setting 2 current setting 1 timer counter control fastlock mo de fastlock e nable cp t hre e - sta t e pd p o larity muxout control pow e r - down 1 counte r r eset control bits initialization latch f i g u re 22. lat c h su mm ar y rev. 0 | page 11 of 20
adf4107 rev. 0 | page 12 of 20 reference counter latch map ldp 0 1 abp2 abp1 0 0 2.9ns 0 1 1.3ns 1 0 6.0ns 1 1 2.9ns r14 r13 r12 .......... r3 r2 r1 0 0 0 .......... 0 0 1 1 0 0 0 .......... 0 1 0 2 0 0 0 .......... 0 1 1 3 0 0 0 .......... 1 0 0 4 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 16380 1 1 1 .......... 1 0 1 16381 1 1 1 .......... 1 1 0 16382 1 1 1 .......... 1 1 1 16383 x = don?t care db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 abp1 abp2 t1 t2 ldp db21 db22 db23 00 x reserved lock de te ct precision test mode bits anti- backlash width 14-bit reference counter control bits divide ratio antibacklash pulsewidth test mode bits should be set to 00 for normal operation. operation three consecutive cycles of phase delay less than 15ns must occur before lock detect is set. five consecutive cycles of phase delay less than 15ns must occur before lock detect is set. both of these bits must be set to 0 for normal operation. f i gure 23. r e ference cou n te r la tch m a p
adf4107 rev. 0 | page 13 of 20 ab counter latch map db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 a6 db21 db22 db23 g1 00 0 1 1 0 f4 (function latch) fastlock enable 11 a6 a5 .......... a2 a1 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 60 1 1 .......... 0 1 61 1 1 .......... 1 0 62 1 1 .......... 1 1 63 xx b13 b12 b11 b3 b2 b1 0 0 0 .......... 0 0 0 0 0 0 .......... 0 0 1 0 0 0 .......... 0 1 0 0 0 0 .......... 0 1 1 3 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 8188 1 1 1 .......... 1 0 1 8189 1 1 1 .......... 1 1 0 8190 1 1 1 .......... 1 1 1 8191 x = don ? t care reserved 13-bit b counter 6-bit a counter control bits cp g a in a counter divide ratio b counter divide ratio not allowed not allowed not allowed these bits are not used by the device and are don't care bits. operation cp gain charge pump current setting 1 is permanently used. charge pump current setting 2 is permanently used. charge pump current setting 1 is used. charge pump current is switched to setting 2. the time spent in setting 2 is dependent on which fastlock mode is used. see function latch description. n = bp + a, p is prescaler value set in the function latch. b must be greater than or equal to a. for continuously adjacent values of (n f ref ), at the output, n min is (p 2 ? p). f i gure 24. a b co un ter l a tc h map
adf4107 rev. 0 | page 14 of 20 function l a tch map p2 p1 0 0 8/9 0 1 16/17 1 0 32/33 1 1 64/65 pd2 pd1 mode 0 x x 1 x0 10 1 11 1 cpi6 cpi5 cp14 cpi3 cpi2 cpi1 3k ? 5.1k ? 11k ? 0 0 0 1.06 0.625 0.289 0 0 1 2.12 1.25 0.580 0 1 0 3.18 1.875 0.870 0 1 1 4.24 2.5 1.160 1 0 0 5.30 3.125 1.450 1 0 1 6.36 3.75 1.730 1 1 0 7.42 4.375 2.020 1 1 1 8.50 5.0 2.320 tc4 tc3 tc2 tc1 00 003 00 017 00 101 1 00 111 5 01 001 9 01 012 3 01 102 7 01 113 1 10 003 5 10 013 9 10 104 3 10 114 7 11 005 1 11 015 5 11 105 9 11 116 3 f4 0 1 1 m3 m2 m1 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 f3 0 1 f2 0 1 f1 0 1 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) f1 pd1 m1 m2 m3 f3 p1 p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4 f5 three-state f5 x 0 1 negative positive prescaler value pow e r - down 2 current setting 2 current setting 1 timer counter control fastlock mo de fastlock e nable cp thre e - sta t e muxout control pow e r - down 1 counte r r eset control bits phase detector polarity counter operation normal r, a, b counters held in reset charge pump output normal fastlock disabled fastlock mode 1 fastlock mode 2 fastlock mode three-state output digital lock detect (active high) n divider output dv dd r divider output n-channel open-drain lock detect serial data output dgnd output timeout (pfd cycles) i cp (ma) asynchronous power-down normal operation asynchronous power-down synchronous power-down ce pin prescaler value pd p o larity f i gure 25. f u nc t i on latc h map
adf4107 rev. 0 | page 15 of 20 initialization latch map p2 p1 0 0 8/9 0 1 16/17 1 0 32/33 1 1 64/65 pd2 pd1 mode 0 x x 1 x0 10 1 11 1 cpi6 cpi5 cp14 cpi3 cpi2 cpi1 3k ? 5.1k ? 11k ? 0 0 0 1.06 0.625 0.289 0 0 1 2.12 1.25 0.580 0 1 0 3.18 1.875 0.870 0 1 1 4.24 2.5 1.160 1 0 0 5.30 3.125 1.450 1 0 1 6.36 3.75 1.730 1 1 0 7.42 4.375 2.020 1 1 1 8.50 5.0 2.320 tc4 tc3 tc2 tc1 00 003 00 017 00 101 1 00 111 5 01 001 9 01 012 3 01 102 7 01 113 1 10 003 5 10 013 9 10 104 3 10 114 7 11 005 1 11 015 5 11 105 9 11 116 3 f4 0 1 1 m3 m2 m1 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 f3 0 1 f2 0 1 f1 0 1 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (1) f1 pd1 m1 m2 m3 f3 p1 p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4 f5 three-state f5 x 0 1 negative positive prescaler value pow e r - down 2 current setting 2 current setting 1 timer counter control fastlock mo de fastlock e nable cp thre e - sta t e muxout control pow e r - down 1 counte r r eset control bits phase detector polarity counter operation normal r, a, b counters held in reset charge pump output normal fastlock disabled fastlock mode 1 fastlock mode 2 fastlock mode three-state output digital lock detect (active high) n divider output dv dd r divider output n-channel open-drain lock detect serial data output dgnd output timeout (pfd cycles) i cp (ma) asynchronous power-down normal operation asynchronous power-down synchronous power-down ce pin prescaler value pd p o larity f i g u re 26. init ia li za t i on l a tc h m a p
adf4107 rev. 0 | page 16 of 20 i i function latch the on-chip function latch is programmed with c2 and c1 set to 1 and 0, respectively. figure 25 shows the input data format for programming the function latch. counter reset db2 (f1) is the counter reset bit. when this bit is 1, the r counter and the ab counters are reset. for normal operation, this bit should be 0. upon powering up, the f1 bit needs to be disabled (set to 0). then, the n counter resumes counting in close alignment with the r counter. (the maximum error is one prescaler cycle). power-down db3 (pd1) and db21 (pd2) provide programmable power- down modes. they are enabled by the ce pin. when the ce pin is low, the device is immediately disabled regardless of the states of pd2 and pd1. in the programmed asynchronous power-down, the device powers down immediately after latching a 1 into the pd1 bit, with the condition that pd2 has been loaded with a 0. in the programmed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. once the power-down is enabled by writing a 1 into pd1 (on condition that a 1 has also been loaded to pd2), then the device will go into power-down on the occurrence of the next charge pump event. when a power-down is activated (either synchronous or asynchronous mode, including ce pin activated power-down), the following events occur: x all active dc current paths are removed. x the r, n, and timeout counters are forced to their load state conditions. x the charge pump is forced into three-state mode. x the digital lock detect circuitry is reset. x the rf in input is debiased. x the reference input buffer circuitry is disabled. x the input register remains active and capable of loading and latching data. muxout control the on-chip multiplexer is controlled by m3, m2, m1 on the adf4107. figure 25 shows the truth table. fastlock enable b t db9 of the function latch is the fastlock enable bit. fastlock is enabled only when this bit is 1. fastlock mode bit db10 of the function latch is the fastlock mode bit. when fastlock is enabled, this bit determines which fastlock mode is used. if the fastlock mode bit is 0, then fastlock mode 1 is selected; and if the fastlock mode bit is 1, then fastlock mode 2 is selected. fastlock mode 1 the charge pump current is switched to the contents of current setting 2. the device enters fastlock by having a 1 written to the cp gain bit in the ab counter latch. the device exits fastlock by having a 0 written to the cp gain bit in the ab counter latch. fastlock mode 2 the charge pump current is switched to the contents of current setting 2. the device enters fastlock by having a 1 written to the cp gain bit in the ab counter latch. the device exits fastlock under the control of the timer counter. after the timeout period determined by the value in tc4?tc1, the cp gain bit in the ab counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. see figure 25 for the timeout periods. t mer counter control the user has the option of programming two charge pump currents. the intent is that current setting 1 is used when the rf output is stable and the system is in a static state. current setting 2 is meant to be used when the system is dynamic and in a state of change (i.e., when a new output frequency is programmed). the normal sequence of events is as follows: the user initially decides what the preferred charge pump currents are going to be. for example, the choice may be 2.5 ma as current setting 1 and 5 ma as current setting 2. at the same time it must be decided how long the secondary current is to stay active before reverting to the primary current. this is controlled by the timer counter control bits, db14?db11 (tc4?tc1) in the function latch. the truth table is given in figure 25. now, to program a new output frequency, the user simply programs the ab counter latch with new values for a and b. at the same time, the cp gain bit can be set to 1, which sets the charge pump with the value in cpi6?cpi4 for a period of time determined by tc4?tc1. when this time is up, the charge pump current reverts to the value set by cpi3?cpi1. at the same time the cp gain bit in the ab counter latch is reset to 0 and is now ready for the next time that the user wishes to change the frequency.
adf4107 rev. 0 | page 17 of 20 note that there is an enable feature on the timer counter. it is enabled when fastlock mode 2 is chosen by setting the fastlock mode bit (db10) in the function latch to 1. charge pump currents cpi3, cpi2, and cpi1 program current setting 1 for the charge pump. cpi6, cpi5, and cpi4 program current setting 2 for the charge pump. the truth table is given in figure 25. prescaler value p2 and p1 in the function latch set the prescaler values. the prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 300 mhz. thus, with an rf frequency of 4 ghz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid. pd polarity this bit sets the phase detector polarity bit. see figure 25. cp three-state this bit controls the cp output pin. with the bit set high, the cp output is put into three-state. with the bit set low, the cp output is enabled. initialization latch the initialization latch is programmed when c2 and c1 are set to 1 and 1. this is essentially the same as the function latch (programmed when c2, c1 = 1, 0). however, when the initialization latch is programmed an additional internal reset pulse is applied to the r and ab counters. this pulse ensures that the ab counter is at load point when the ab counter data is latched and the device will begin counting in close phase alignment. if the latch is programmed for synchronous power-down (ce pin is high; pd1 bit is high; pd2 bit is low), the internal pulse also triggers this power-down. the prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse and so close phase alignment is maintained when counting resumes. when the first ab counter data is latched after initialization, the internal reset pulse is again activated. however, successive ab counter loads after this will not trigger the internal reset pulse. device programming after initial power-up after initially powering up the device, there are three ways to program the device. initialization latch method apply v dd . program the initialization latch (11 in two lsbs of input word). make sure that the f1 bit is programmed to 0. next, do a function latch load (10 in two lsbs of the control word), making sure that the f1 bit is programmed to a 0. then do an r load (00 in two lsbs). then do an ab load (01 in two lsbs). when the initialization latch is loaded, the following occurs: 1. the function latch contents are loaded. 2. an internal pulse resets the r, ab, and timeout counters to load-state conditions and also three-states the charge pump. note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. 3. latching the first ab counter data after the initialization word will activate the same internal reset pulse. successive ab loads will not trigger the internal reset pulse unless there is another initialization. ce pin method apply v dd . bring ce low to put the device into power-down. this is an asychronous power-down in that it happens immediately. program the function latch (10). program the r counter latch (00). program the ab counter latch (01). bring ce high to take the device out of power-down. the r and ab counters will now resume counting in close alignment. note that after ce goes high, a duration of 1 s may be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. ce can be used to power the device up and down in order to check for channel activity. the input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after v dd was initially applied. counter reset method apply v dd . do a function latch load (10 in two lsbs). as part of this, load 1 to the f1 bit. this enables the counter reset. do an r counter load (00 in two lsbs). do an ab counter load (01 in two lsbs). do a function latch load (10 in two lsbs). as part of this, load 0 to the f1 bit. this disables the counter reset. this sequence provides the same close alignment as the initialization method. it offers direct control over the internal reset. note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down.
adf4107 rev. 0 | page 18 of 20 appli c ations local os cillator for lmds b a se station transmitter f i gur e 27 be lo w s h o w s t h e ad f4107 bein g us ed wi t h a v c o t o p r o d uce t h e l o f o r a n lmds b a s e s t a t ion. the r e fer e n c e i n p u t sig n al is a pplie d t o t h e cir c ui t a t fref in a n d , in t h i s cas e , is t e r m ina t e d i n 50 ?. a ty p i ca l b a s e st a t ion sys t em w o u l d ha v e ei ther a t c x o o r an o c x o dr i v in g t h e re f e re nc e i n put w i t h out a n y 5 0 ? te r m i n a t i o n . t o ha ve a chan nel sp acin g o f 1 mh z a t t h e o u t p u t , t h e 10 mhz re f e re nc e i n put m u st b e d i v i d e d by 1 0 , u s i n g t h e on - c h i p re f e re nc e d i v i d e r of t h e a d f 4 1 0 7 . the c h a r g e p u m p o u t p u t o f the ad f4107 (p in 2) dr i v es th e lo o p f i l t er . i n ca lc u l a t in g t h e lo op f i l t er co m p onen t val u es, a n u m b er o f i t ems n e e d t o b e consider e d . i n t h i s exa m ple , t h e lo o p f i l t er was desig n e d s o t h a t t h e o v eral l phas e ma rg in fo r t h e sys t em w o u l d b e 45. o t h e r pll sy st e m sp e c if ic a t io n s a r e: k d = 5.0 ma k v = 80 mh z/v l o o p b a nd w i d t h = 70 khz f pf d = 1 m h z n = 6300 e x t r a refer e n c e s p ur a t te n u a t i o n = 10 db a l l o f t h es e sp e c if ica t ion s a r e ne e d e d an d us e d t o der i v e t h e l o op f i lte r c o m p one n t v a lu e s s h ow n i n f i g u re 2 7 . f i gur e 27 g i v e s a typ i cal phas e n o is e p e r f o r ma n c e o f ?83 db c/h z a t 1 kh z o f fs et f r o m the ca r r ier . s p urs a r e bet t er tha n ?70 db c. the lo o p f i l t er ou t p ut dr i v es t h e v c o , w h ich, i n t u r n , is fe d b a ck t o t h e rf i n p u t o f t h e p l l syn t h e si zer an d als o dr i v es t h e rf o u t p ut t e r m i n a l . a t - cir c ui t co nf igura t io n pr o v ides 50 ? ma tch i ng b e t w e e n t h e v c o output , t h e r f output , and t h e r f in t e r m inal o f th e syn t h e sizer . i n a pll sy st e m , i t is im p o r t a n t t o k n o w w h en t h e sy st em is in lo ck. i n f i gur e 2 7 , t h is is acco m p lish e d b y usin g t h e m u x o u t sig n al f r o m th e syn t h e sizer . th e mux o ut p i n ca n be pro g r a mme d to mon i tor v a r i ou s i n te r n a l s i g n a l s i n t h e syn t h e sizer . one o f t h es e is t h e ld o r lo ck dete c t sig n al . adf4107 ce clk data le 1000pf 1000pf refin 100pf cp muxout cp gnd agnd dgnd 100pf 820pf 47pf 100pf 51 ? 1.7k ? 7.5k ? 100pf 18 ? note decoupling capacitors (0.1 f/10pf) on av dd , dv dd , v p of the adf4107 and on v cc of the v956me01 have been omitted from the diagram to aid clarity. s p i comp at ibl e s e r ial bus r set rf in a rf in b av dd dv dd v p fref in v dd v p lock detect v cc v956me01 1, 3, 4, 5, 7, 8, 9, 11, 12, 13 18 ? 18 ? 100pf rf out 5.1k ? 7 15 16 8 2 14 6 5 1 9 4 3 14 2 10 51 ? f i g u re 27. 6. 3 g h z l o c a l o s ci ll at or u s ing t h e a d f 4 1 0 7
adf4107 rev. 0 | page 19 of 20 interfacing the ad f4107 has a sim p le s p i? co m p a t i b le s e r i al in t e r f ace f o r w r i t i n g t o t h e d e v i c e . c l k , d a t a , a n d l e c o n t r o l t h e d a t a t r a n sfer . w h en le (l a t ch enab le) g o es hig h , t h e 24 b i ts t h a t h a v e been c l ock e d in t o th e in p u t r e gi s t e r o n ea ch ri s i n g ed g e o f clk wi l l g e t t r an sfer r e d t o t h e a p p r o p r i a t e la t c h. s e e f i gur e 2 f o r th e ti m i n g di a g ra m a n d t a b l e 5 f o r th e l a t c h tr u t h ta b l e . the max i m u m a l lo wa b l e s e r i a l clo c k ra te is 20 mh z. t h is m e a n s th a t th e m a xi m u m u p da t e ra t e pos s i b le f o r th e de v i ce i s 833 kh z o r o n e u p da te ever y 1.2 s. this is cer t a i nl y m o r e tha n ade q u a te fo r sys t em s tha t ha v e typ i cal lo c k tim e s in h u ndr e d s of micr o s e c o n ds . aduc812 int e rface f i gur e 28 s h o w s th e in t e r f ace betw een t h e ad f 4107 a nd the aduc812 m i croc o n v e r t er?. s i n c e t h e aduc8 12 is bas e d o n an 8051 co r e , this in t e r f ace c a n be us ed wi t h an y 8051 bas e d micr o c o n tr ol ler . the m i cr oc o n v e r t er is s e t u p f o r s p i mas t er m o de wi t h cph a = 0. t o ini t i a t e t h e op era t ion, t h e i / o p o r t dr i v in g le is b r o u g h t lo w . e a c h la t c h o f th e adf4107 n eeds a 24-b i t w o r d . t h is is acco m p lishe d b y wr i t in g t h r e e 8-b i t b y t e s f r o m t h e micr o c o n v e r t er t o t h e de vic e . w h en t h e t h ird b y t e has b e e n w r i tte n, t h e l e i n put s h ou l d b e b r ou g h t h i g h to c o m p l e te th e tra n sf e r . on f i rs t a p p l ying p o w e r t o th e ad f4107, i t nee d s f o ur wr i t es (o n e each t o t h e ini t ializa tio n la t c h, f u n c t i o n l a tc h, r co un ter l a tc h , a n d n c o u n te r l a tc h ) for t h e out p ut to b e c o me a c t i ve. i/o p o r t lin e s on the adu c 812 a r e als o us ed t o co n t r o l p o w e r - do wn (ce i n p u t ) a nd to dete c t lo ck (mu x out co nf igur e d as lo c k det e c t an d p o l l ed b y th e p o r t in p u t). w h en o p era t i n g in t h e m o de des c r i b e d , t h e maxim u m scl o ck ra te of th e adu c 812 is 4 mh z. this m e an s tha t the max i m u m ra te a t w h ich t h e ou tp u t f r e q uen c y c a n b e chan ge d wil l be 166 kh z. clk data le ce muxout (lock detect) mosi adf4107 sclock i/o ports aduc812 f i gur e 2 8 . aduc812 to adf410 7 int e r f a c e adsp2181 int e rface f i gur e 29 s h o w s th e in t e r f ace betw een t h e ad f 4107 a nd the ads p 21xx dig i tal s i g n al p r o c es s o r . the ad f4 107 n eeds a 2 4 - b i t se ri al w o r d f o r ea c h l a t c h w r i t e . th e e a si e s t wa y t o acco m p lish t h is usin g t h e adsp 21xx fa mi ly is t o us e t h e au t o b u f f e r e d t r a n s m i t m o d e o f o p e r at i o n w i t h a l t e r n at e f r am i n g . t h i s prov i d e s a me ans for t r ans m i t t i n g an e n t i re bl o c k o f se ri al d a ta bef o r e a n i n t e rr u p t i s g e n e ra t e d . s e t u p th e w o r d len g th f o r 8 b i ts a nd us e thr e e m e m o r y lo ca tion s f o r eac h 24-b i t w o r d . t o p r og ra m e a ch 24 -b i t la t c h, s t o r e t h e t h r e e 8-b i t b y t e s, ena b le t h e a u t o b u f f er e d mo de , a nd t h en wr i t e to t h e t r a n smi t r e g i st er o f t h e ds p . this last o p era t ion in i t ia t e s t h e a u t o b u f f er tra n sf e r . clk data le ce muxout (lock detect) dt adf4107 sclk i/o flags adsp21xx tfs f i gur e 2 9 . adsp -21xx t o adf410 7 int e r f a c e pcb design guidelines for chip scale pac k ag e the lan d s on t h e chi p s c ale p a cka g e (c p - 20) a r e r e c t a n gu la r . the p r in te d cir c ui t b o a r d p a d for t h es e sh o u ld b e 0.1 mm lo n g e r th a n th e pa c k a g e la n d len g th a n d 0. 05 m m w i d e r th a n t h e p a cka g e land w i d t h. th e l a nd sh o u ld b e ce n t er e d o n t h e p a d . this wi l l ens u r e t h a t t h e s o lder j o in t si ze is maxi mi ze d . th e b o t t om o f t h e chi p s c ale p a cka g e has a ce n t ral t h er mal p a d . the t h er mal p a d o n t h e p r i n t e d cir c ui t b o a r d sh o u ld b e a t le ast a s la r g e a s th i s exposed pa d . on th e p r i n t e d ci r c ui t boa r d , th e r e s h o u ld b e a cle a ra n c e o f a t le as t 0.25 mm b e tw e e n t h e t h er mal p a d an d t h e in ner e d ges o f t h e p a d p a t t er n. thi s wi l l ensur e t h a t shor t i ng i s a v oi d e d. ther mal v i as ma y b e us e d on t h e p r i n t e d cir c ui t b o a r d t h er mal p a d t o im p r o v e t h er mal p e r f o r ma nce o f t h e p a cka g e . i f vi as a r e used , th ey s h o u l d b e in co r p o r a t ed in th e th e r m a l pa d a t 1. 2 mm p i t c h g r id . th e v i a diamet er sho u ld b e b e tw e e n 0.3 mm an d 0.33 mm and t h e via b a r r e l s h ou ld be pla t ed wi th 1 oz. co p p er to plu g t h e v i a. the us er sho u ld co nne c t t h e p r i n te d cir c ui t b o ar d t h er ma l p a d to a g nd .
adf4107 outline dimensions 16 9 8 1 pi n 1 se a t i n g pl a n e 8 0 4. 50 4. 40 4. 30 6. 40 bs c 5. 10 5. 00 4. 90 0. 65 bs c 0 .1 5 0 .0 5 1. 20 ma x 0. 2 0 0. 0 9 0. 75 0. 60 0. 45 0. 30 0. 19 c o p l an ar i t y 0. 10 c o m p l i a n t t o j e d e c s t a n d a r d s m o - 153a b f i g u re 30. 16-l e ad thin shr i nk s m al l o u t line p a ck age [ t ssop ] (ru-16)d i m ens i ons sh o w n in m i l l i m eters 1 20 5 6 11 16 15 b o tto m vi ew 10 2. 25 2. 10 s q 1. 95 0. 75 0. 55 0. 35 0. 30 0. 23 0. 18 0. 50 bs c 12 m a x 0. 20 re f 1. 00 max 0. 65 no m 0. 05 0. 02 0. 00 1. 0 0 0. 90 0. 80 sea t i n g pl a n e pi n 1 i ndi c a t o r to p vi ew 3. 75 bs c s q 4. 0 bsc sq co p l an ari ty 0. 08 c o mpl i a n t t o j e d e c s t a n d a r d s mo -2 2 0 -vg g d -1 0. 6 0 ma x 0. 60 ma x f i gure 31. 20-l e ad f r a m e ch ip s c a l e p a ckage [l f c sp ] ( c p - 2 0 ) d im ensio n s sho wn i n mi ll im eter s esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity. orderi ng guide model temperature r a nge package option adf4107bru C40c to + 85c ru-16 adf4107bruCr eel C40c to + 85c ru-16 adf4107bruCr eel7 C40c to + 85c ru-16 ADF4107BCP C40c to + 85c cp-20 ADF4107BCPCr eel C40c to + 85c cp-20 ADF4107BCPCr eel7 C40c to + 85c cp-20 r u = th i n sh ri n k s m a ll out l i n e pa cka g e (tsso p) cp = ch i p sca l e pa c k a g e c o ntact the f a ctory f o r chip avail abil ity. note that aluminu m bond wire should not be u s ed with the adf4107 die. ? 2003 anal og de vices, inc. all ri ghts rese rved. tra d emarks a n d registered tra d ema r ks are the proper ty of th eir respectiv e co mpan ies. c03338-0-5/03(0) rev. 0 | page 20 of 20

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